This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-245029, filed Aug. 11, 2000, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device, and particularly to a non-volatile semiconductor memory device having a memory cell array suitable for high density and high integration.
2. Description of the Related Art
A flash memory is well known as a non-volatile semiconductor memory device, which enables electric re-writing of data and is suitable for high density and large capacity. Generally, in a flash memory, a plurality of memory cells each having a MOS transistor structure with a stacked gate in which a charge storage layer and a control gate are layered are provided in a matrix. A word-line signal is inputted to the control gates of these memory cells, and a bit-line signal is inputted to sources or drains of the memory cells.
FIG. 1A is a plan view showing the structure of the memory cell array in a NOR-type flash memory. FIG. 1B is a cross-sectional view cut along the line 1Bxe2x80x941B of the memory cell array shown in FIG. 1A.
As shown in FIG. 1B, a charge storage layer 103 is formed on a p-type silicon semiconductor substrate 101 with a tunnel gate insulating film 102 inserted therebetween. A control gate 105 is formed on the charge storage layer 103 with an inter-gate insulating film 104 inserted therebetween. Each memory cell has a stacked gate in which the charge storage layer 103 and the control gate 105 are layered. This stacked gate is processed vertically in a self-aligning manner such that side end parts thereof are aligned.
Also, the memory cells each have a source region 106A and a drain region 106B which are formed of an n-type diffusion layer. The source region 106A and the drain region 106B are formed in the semiconductor substrate 101 at both sides of the stacked gate. One of the source region 106A and the drain region 106B is connected to a bit line 108 through a bit-line contact material 107, and the other is connected to a common source line 110 through a common source line contact material 109.
A structure interposing a contact material like the bit line, a structure directly connected through a buried metal line, a structure in which sources of memory cells of each bit line are connected with use of a diffusion layer, or the like is widely used to connect the common source line 110 and the source region 106A to each other. The case of connection to the common source line 110 through the contact material 109 is now shown.
The bit-line contact material 107 described above has a side end part adjacent to a stacked gate and is constructed in a so-called self-aligned contact structure in which a part of the contact material 107 extends over the stacked gate, at its connecting part to a bit line 108. This structure is adopted to eliminate a dimensional margin between the bit-line contact material 107 and the stacked gate, so that the memory cell array can be downsized.
To attain the self-aligned contact structure, the stacked gate is covered with a cap material 111, e.g., a silicon nitride film. In particular, the cap material 111 is formed thick on the control gate 105. In this manner, the contact material 107 buried in a contact hole and the control gate 105 are prevented from being short-circuited. A conductive material such as low-resistance poly-silicon or metal material is used for the contact material 107. Note that the reference 112 denotes an inter-layer insulating film made of a BPSG film or the like.
The common source-line contact material 109 is not constructed in a self-aligned contact structure but a special margin is maintained between the stacked gate and the contact material 109. This is because a potential difference of about 10 V occurs in a NOR-type memory when erasure operation is carried out. Since the withstanding voltage at this time is maintained, it is difficult to make a self-aligned contact.
FIG. 2A is a plan view showing the structure of a memory cell array in a NAND-type flash memory. FIG. 2B is a cross-sectional view of the memory cell array shown in FIG. 2A, cut along the line 2Bxe2x80x942B.
A plurality of memory cells are connected in series, with sources and drains shared between each other, thereby to construct a NAND column. At both ends of the NAND column, selection transistors are provided. Of the selection transistors provided at both ends, a drain or source of one selection transistor is connected to a bit line 208 through a bit-line contact material 207. A drain or source of the other selection transistor is connected to a common source line 210 through a common source line contact material 209.
The memory cells and selection transistors have stacked gates in which charge storage layer 203 and the control gate 205 are layered, like the NOR-type memory cell. The charge storage layer 203 of the selection transistor or the charge storage layer 203 and the control gate 205 are connected to the gate signal line at another portion than the region shown in the figure.
The bit-line contact material 207 has a side end part adjacent to a stacked gate and is constructed in a so-called self-aligned contact structure in which a part of the contact material 207 extends over the stacked gate, at its connecting part to a bit line 208. This structure is adopted to eliminate a dimensional margin between the bit-line contact material 207 and the stacked gate, so that the memory cell array can be downsized. To attain the self-aligned contact structure, the stacked gate is covered with a cap material 211, e.g., a silicon nitride film. In particular, the cap material 211 on the control gate 205 is formed thick on the control gate 205. In this manner, the contact material 207 buried in a contact hole and the control gate 205 are prevented from being short-circuited. A conductive material such as low-resistance poly-silicon or metal material is used for the contact material 207.
Like the bit line contact material 207, the common source line contact material 209 is also constructed in a self-aligned contact structure, in the NAND type memory. This is because only a small potential difference (about 3 V) exists between the common source line 210 and the control gate 205 of the selection transistor adjacent to the source line in the NAND type memory, so there will not appear a problem of dielectric breakdown even if a self-aligned contact is made.
The self-aligned contact structure is adopted to reduce the dimensional margin between the contact material and the gate, thereby to shorten the cell array length in the direction of the bit-line 208. The method of using the self-aligned contact structure to shorten the cell array length is very effective regardless of whether the memory cell is of the NAND type or NOR type.
In accordance with reduction of the design rule, the self-aligned contact structure is considered to have much higher effectiveness as the gate length is shortened. This is because it is difficult to scale variants and the like at the time of lithography, at the same ratio as that of the reduction of the gate length. Therefore, the distance between the contact material and the gate is not reduced to the level as that of the gate length.
Formation of the bit line contact material 207 and the common source line contact material 209 is normally performed as follows. At first, a stacked gate is buried by an inter-layer insulating film 213 such as a BPSG film or the like. Flattening processing is carried out by CMP or the like. The BPSG film is a film which attains an improved melting property by mixing impurities such as boron, phosphors, and the like into a silicon dioxide film.
Thereafter, contact holes are opened by dry etching. When these contact holes are opened, the cap material 211 on the control gate 205 is thinned or is perfectly removed so that the control gate 205 is exposed, if the etching election ratio between the cap material 211 covering the control gate 205 and the inter-layer insulating film 213 is not high. In this case, a short-circuiting defect occurs when a contact material is buried. Therefore, a silicon-dioxide-based film is widely used for the inter-layer insulating film 213, and a silicon-nitride-based film which attains a relatively high selection ratio relative to the silicon-dioxide-based film is widely used for the cap material 211.
However, if the silicon-nitride-based film is formed covering the gate of a transistor, a stack insulating film structure constructed by a gate film mainly made of a silicon dioxide film and a silicon nitride film is formed on the diffusion layer in the side of the gate. Therefore, hot electrons generated at channels during operation of a pentode of a transistor are caught by the inter-layer insulating film interface (the interface between the gate insulating film and the silicon nitride film), causing an electronic trap. It is generally known that modulation of an ON-current of a transistor, change of a threshold voltage, deterioration of a surface junction withstanding voltage, or the like is caused if this electronic trap thus occurs.
The flash memory has a memory cell array and a peripheral circuit. The peripheral circuit is a circuit which generates a signal for driving the memory cell array and is formed outside the region of the memory cell array. This peripheral circuit, for example, generates a control gate signal and a bit-line signal. In many cases, the peripheral transistor is also constructed in a gate structure similar to that of the memory cell, to reduce processing steps and to share processes, in the flash memory described above. Therefore, the peripheral transistor is formed into a shape in which the gate is covered with a cap material and causes deterioration of characteristics at high possibility, like the memory cell and the selection transistor.
To solve this problem, a structure in which a silicon-dioxide-based film is sandwiched between a silicon nitride film and a gate has been proposed. The object of sandwiching a silicon-dioxide-based film between a thin gate insulating film on a diffusion layer and the silicon nitride film is to widen the distance between the diffusion layer and the silicon nitride film to reduce caught hot electrons.
However, it is difficult to realize simultaneously the structure in which a silicon-dioxide-based film is sandwiched between the silicon nitride film and the gate, and the structure self-aligned contact structure described above.
FIGS. 3A, 3B, 4A, and 4B are cross-sectional views showing steps of forming a self-aligned contact in a structure in which a silicon-dioxide-based film is sandwiched between a silicon nitride film and a stacked gate.
After forming a stacked gate, a silicon dioxide film 214 is formed with a thickness of, for example, about 200 xc3x85, on the stacked gate. Further, a silicon nitride film 215 is formed with a thickness of, for example, about 400 xc3x85, on the silicon dioxide film 214. Further, an interlayer insulating film 213 is formed the above-described silicon nitride film 215. Thereafter, as shown in FIG. 3A, the interlayer insulating film 213 is flattened by CMP or the like.
Subsequently, a resist film 216 is applied onto the structure shown in FIG. 3A. Thereafter, as shown in FIG. 3B, a part of the resist film which corresponds to a contact part is opened by a lithography method.
Next, the interlayer insulating film 213 is etched by dry etching, using the resist film 216 as a mask, as shown in FIG. 4A. At this time, the silicon nitride film 215 and the silicon nitride film of the cap material 211 are etched in correspondence with the etching selection ratio between the interlayer insulating film 213 and the silicon nitride film. Generally, etching is concentrated on end parts of the gate, so that the film is reduced more. Therefore, a silicon dioxide film 214 is exposed at a part. Thereafter, interfacial cleaning is performed on the structure shown in FIG. 4A. In the worst case, the silicon dioxide film 214 can be etched back.
Thereafter, a contact material 217, e.g., metal such as a low-resistance polysilicon or tungsten (W) is buried. Further, as shown in FIG. 4B, the contact material 217 is flattened to finish a contact.
In the manufacturing method described above, the silicon dioxide film 214 in the contact hole is etched back. As a result, the contact material 217 (buried-electrode material) enters into the etched-back part, so that the possibility of short-circuiting between the contact material 217 and the control gate 205 rises. Hence, in a conventional technique, it is difficult to use the structure in which the silicon dioxide film 214 is sandwiched between the silicon nitride film 215 and the stacked gate to improve the reliability, together with the self-aligned contact structure.
As another problem in case of using the self-aligned contact structure for the bit-line contact part and the common source line contact part, residual parts of a film on gap parts of an element separation insulating film.
FIG. 5 is a cross-sectional view in case where the memory cell array shown in FIG. 4B is cut along the line 5xe2x80x945 in FIG. 2A.
As shown in FIG. 5, on the semiconductor region sandwiched by the element separation insulation films 217, the bit-line contact material 207 and the semiconductor region are electrically connected with each other. On the side surfaces in both sides of the element separation insulating film 217, the silicon dioxide film 214 and the silicon nitride film 215 remain like spacers. These residues greatly reduce the contact area between the bit-line contact material 207 and the semiconductor region. Reduction of the contact area involves effective lowering of the cell current, so that the silicon nitride film 215 on the semiconductor region must be perfectly removed when opening the contact hole.
On the other hand, however, the silicon nitride film 215 on the control gate 205 must be left for a self-aligned contact. Thus, there is a trade-off that the silicon nitride film 215 on the semiconductor region must be removed while the silicon nitride film 215 on the control gate 205 must be left, so that the processing margin greatly decreases.
The above problem is conspicuous particularly when the element separation insulating film 217 is formed to be higher than the semiconductor region. If element separation is carried out with use of a self-alignment STI (Shallow Trench Isolation) method, the element separation insulating film 217 is formed to be higher than the semiconductor substrate, so that its influence is greater than an element separation structure based on a LOCOS method. The above-described self-alignment STI method is a method of forming an element separation region with use of a shallow trench formed by a self-alignment method. More specifically, in this method, a trench is formed after depositing a charge storage layer. Further, an insulating material is buried in the trench, thereby to form an element separation structure.
Also, if low-resistance polysilicon is used as a contact material to be buried in the bit-line contact hole, there is a characteristic that ohmic contact is obtained between the contact material and the semiconductor region, without using a barrier metal material such as Ti, TiN, or the like as a buffer film and without causing the problem of abnormal contact resistance or increase of junction leakage even when the impurity density of the semiconductor region (diffusion layer) is relatively low.
Therefore, the contact resistance increases to be greater than in the case of using metal material for the contact material. However, there is a case that the contact part using the same buried material as that of the bit-line contact part is used for a peripheral transistor forming part of a peripheral circuit, for the purpose of reducing the dimensional margin between the contact material and the semiconductor region, to down-size the elements.
In this case, the contact hole of the high-withstanding-voltage-based transistor needs to be opened at the same time when the contact hole of the bit-line contact part is opened. However, the gate insulating film of the high-withstanding-voltage-based transistor is much thicker, compared with the memory cell. For example, the film thickness of the gate insulating film of the high-withstanding-voltage-based transistor is 150 xc3x85 to 200 xc3x85 in case of an NOR-type flash memory or 300 xc3x85 to 400 xc3x85 in case of an NAND-type flash memory, in relation to the film thickness of the gate insulating film of the memory cell which is about 100 xc3x85. Therefore, the silicon nitride film on the diffusion layer needs to be opened, and further, the gate insulating film needs to be etched by 150 xc3x85 to 400 xc3x85, to open perfectly a contact hole in the diffusion layer of the high-withstanding-voltage-based transistor.
However, if additional etching is carried out, a defect occurs in that the film of the cap material on the control gate is reduced at the bit-line contact part or the element separation film partially overlapping the contact part is etched back. That is, in case where a self-aligned contact structure is adopted to form the bit-line contact part, there is a problem that it is very difficult to form the contact part of a peripheral transistor through the same process as that of forming the bit-line contact part.
As has been described above, there is a problem that techniques which have been conventionally proposed cannot be used in case where the bit-line contact part is constructed in a self-aligned contact structure. That is, a conventional non-volatile semiconductor memory device has a problem in that the above-described techniques for attaining high reliability and for downsizing peripheral transistors cannot be used if a self-aligned contact structure is adopted at the bit-line contact part.
According to an aspect of the present invention, a non-volatile semiconductor memory device comprises: a semiconductor body of a first conductivity type; first and second semiconductor regions of a second conductivity type, formed apart from each other on the semiconductor body; a stacked gate formed with a gate insulating film inserted thereunder, on the semiconductor body between the first and second semiconductor regions, the stacked gate having a first side surface, a second side surface opposed to the first side surface, and an upper surface; an interlayer insulating film formed above the semiconductor body; a contact material buried to be adjacent to the first side surface of the stacked gate, in the interlayer insulating film, the contact material contacting the first semiconductor region; a first insulating film formed on the second side surface and the upper surface, except the first side surface of the stacked gate adjacent to the contact material; and a second insulating film formed on the first side surface adjacent to the contact material, and the first insulating film.